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38 Treffer

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  1. Detailansicht für Treffer 1 öffnen
    Design Methodology for an All CMOS Bandgap Voltage Reference Circuit
    Madeira, Ricardo ; Paulino, Nuno ; et al.
    In: IFIP Advances in Information and Communication Technology ; 8th Doctoral Conference on Computing, Electrical and Industrial Systems (DoCEIS) ; https://hal.inria.fr/hal-01629561 ; 8th Doctoral Conference on Computing, 2017
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  2. Detailansicht für Treffer 2 öffnen
    Design Methodology for an All CMOS Bandgap Voltage Reference Circuit
    Madeira, Ricardo ; Paulino, Nuno ; et al.
    In: IFIP Advances in Information and Communication Technology ; 8th Doctoral Conference on Computing, Electrical and Industrial Systems (DoCEIS) ; https://hal.inria.fr/hal-01629561 ; 8th Doctoral Conference on Computing, 2017
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  3. Detailansicht für Treffer 3 öffnen
    A Simple Analysis to Determine the Limits of a CMOS Technology to Implement SC DC-DC Converters
    Madeira, Ricardo ; Paulino, Nuno ; et al.
    In: IFIP Advances in Information and Communication Technology ; 11th Doctoral Conference on Computing, Electrical and Industrial Systems (DoCEIS) ; https://hal.inria.fr/hal-03741562 ; 11th Doctoral Conference on Computing, 2020
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  4. Detailansicht für Treffer 4 öffnen
    A 65 nm CMOS Synthesizable Digital Low-Dropout Regulator Based on Voltage-to-Time Conversion with 99.6% Current Efficiency at 10-mA Load
    Ojima, Naoki ; Nakura, Toru ; et al.
    In: IFIP Advances in Information and Communication Technology ; 26th IFIP/IEEE International Conference on Very Large Scale Integration - System on a Chip (VLSI-SoC) ; https://hal.inria.fr/hal-02321770 ; 26th IFIP/IEEE International Conference on Very Large Scale Integration - System on a Chip (VLSI-SoC), Oct 2018, Verona, Italy. pp.1-13, ⟨10.1007/978-3-030-23425-6_1⟩, 2018
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  5. Detailansicht für Treffer 5 öffnen
    A 65 nm CMOS Synthesizable Digital Low-Dropout Regulator Based on Voltage-to-Time Conversion with 99.6% Current Efficiency at 10-mA Load
    Ojima, Naoki ; Nakura, Toru ; et al.
    In: IFIP Advances in Information and Communication Technology ; 26th IFIP/IEEE International Conference on Very Large Scale Integration - System on a Chip (VLSI-SoC) ; https://hal.inria.fr/hal-02321770 ; 26th IFIP/IEEE International Conference on Very Large Scale Integration - System on a Chip (VLSI-SoC), Oct 2018, Verona, Italy. pp.1-13, ⟨10.1007/978-3-030-23425-6_1⟩, 2018
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  6. Detailansicht für Treffer 6 öffnen
    Functional comparison of acoustic admittance measurements with a CMOS-compatible p-v microprobe and a reference one
    Stanzial, D. ; Buiat, M. ; et al.
    2014
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  7. Detailansicht für Treffer 7 öffnen
    A Multi-criteria Decision Making Approach for Prioritization of the Common Market Organization Policy Measures in North Macedonia
    Janeska Stamenkovska, Ivana ; Dimitrievski, Dragi ; et al.
    2021
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  8. Detailansicht für Treffer 8 öffnen
    Evaluating the Impact of Resistive Defects on FinFET-Based SRAMs
    Copetti, Thiago ; Medeiros, Guilherme ; et al.
    In: IFIP Advances in Information and Communication Technology ; 25th IFIP/IEEE International Conference on Very Large Scale Integration - System on a Chip (VLSI-SoC) ; https://hal.inria.fr/hal-02319796 ; 25th IFIP/IEEE International Conference on Very Large Scale Integration - System on a Chip (VLSI-SoC), Oct 2017, Abu Dhabi, United Arab Emirates. pp.22-45, ⟨10.1007/978-3-030-15663-3_2⟩, 2017
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  9. Detailansicht für Treffer 9 öffnen
    Evaluating the Impact of Resistive Defects on FinFET-Based SRAMs
    Copetti, Thiago ; Medeiros, Guilherme ; et al.
    In: IFIP Advances in Information and Communication Technology ; 25th IFIP/IEEE International Conference on Very Large Scale Integration - System on a Chip (VLSI-SoC) ; https://hal.inria.fr/hal-02319796 ; 25th IFIP/IEEE International Conference on Very Large Scale Integration - System on a Chip (VLSI-SoC), Oct 2017, Abu Dhabi, United Arab Emirates. pp.22-45, ⟨10.1007/978-3-030-15663-3_2⟩, 2017
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  10. Detailansicht für Treffer 10 öffnen
    Logic Synthesis for Silicon and Beyond-Silicon Multi-gate Pass-Logic Circuits
    Tenace, Valerio ; Calimera, Andrea ; et al.
    In: IFIP Advances in Information and Communication Technology ; 24th IFIP/IEEE International Conference on Very Large Scale Integration - System on a Chip (VLSISOC) ; https://hal.inria.fr/hal-01675195 ; 24th IFIP/IEEE International Conference on Very Large Scale Integration - System on a Chip (VLSISOC), Sep 2016, Tallinn, Estonia. pp.60-82, ⟨10.1007/978-3-319-67104-8_4⟩, 2016
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  11. Detailansicht für Treffer 11 öffnen
    Enabling Internet-of-Things with Opportunities Brought by Emerging Devices, Circuits and Architectures
    Li, Xueqing ; Ma, Kaisheng ; et al.
    In: IFIP Advances in Information and Communication Technology ; 24th IFIP/IEEE International Conference on Very Large Scale Integration - System on a Chip (VLSISOC) ; https://hal.inria.fr/hal-01675201 ; 24th IFIP/IEEE International Conference on Very Large Scale Integration - System on a Chip (VLSISOC), Sep 2016, Tallinn, Estonia. pp.1-23, ⟨10.1007/978-3-319-67104-8_1⟩, 2016
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  12. Detailansicht für Treffer 12 öffnen
    Logic Synthesis for Silicon and Beyond-Silicon Multi-gate Pass-Logic Circuits
    Tenace, Valerio ; Calimera, Andrea ; et al.
    In: IFIP Advances in Information and Communication Technology ; 24th IFIP/IEEE International Conference on Very Large Scale Integration - System on a Chip (VLSISOC) ; https://hal.inria.fr/hal-01675195 ; 24th IFIP/IEEE International Conference on Very Large Scale Integration - System on a Chip (VLSISOC), Sep 2016, Tallinn, Estonia. pp.60-82, ⟨10.1007/978-3-319-67104-8_4⟩, 2016
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  13. Detailansicht für Treffer 13 öffnen
    Enabling Internet-of-Things with Opportunities Brought by Emerging Devices, Circuits and Architectures
    Li, Xueqing ; Ma, Kaisheng ; et al.
    In: IFIP Advances in Information and Communication Technology ; 24th IFIP/IEEE International Conference on Very Large Scale Integration - System on a Chip (VLSISOC) ; https://hal.inria.fr/hal-01675201 ; 24th IFIP/IEEE International Conference on Very Large Scale Integration - System on a Chip (VLSISOC), Sep 2016, Tallinn, Estonia. pp.1-23, ⟨10.1007/978-3-319-67104-8_1⟩, 2016
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  14. Detailansicht für Treffer 14 öffnen
    Fully-Autonomous SoC Synthesis Using Customizable Cell-Based Analog and Mixed-Signal Circuits Generation
    Ajayi, Tutu ; Kamineni, Sumanth ; et al.
    In: IFIP Advances in Information and Communication Technology ; 28th IFIP/IEEE International Conference on Very Large Scale Integration - System on a Chip (VLSI-SoC) ; https://hal.inria.fr/hal-03759730 ; 28th IFIP/IEEE International Conference on Very Large Scale Integration - System on a Chip (VLSI-SoC), Oct 2020, Salt Lake City, UT, United States. pp.65-85, ⟨10.1007/978-3-030-81641-4_4⟩, 2020
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  15. Detailansicht für Treffer 15 öffnen
    Fully-Autonomous SoC Synthesis Using Customizable Cell-Based Analog and Mixed-Signal Circuits Generation
    Ajayi, Tutu ; Kamineni, Sumanth ; et al.
    In: IFIP Advances in Information and Communication Technology ; 28th IFIP/IEEE International Conference on Very Large Scale Integration - System on a Chip (VLSI-SoC) ; https://hal.inria.fr/hal-03759730 ; 28th IFIP/IEEE International Conference on Very Large Scale Integration - System on a Chip (VLSI-SoC), Oct 2020, Salt Lake City, UT, United States. pp.65-85, ⟨10.1007/978-3-030-81641-4_4⟩, 2020
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  16. Detailansicht für Treffer 16 öffnen
    Coupled NIRT / 3D-DIC for a FEMU identification of the thermo-mechanical behavior of Zr-4 claddings under simulated Reactivity Initiated Accident
    Jailin, T ; Tardif, Nicolas ; et al.
    In: Residual Stress, Thermomechanics & Infrared Imaging and Inverse Problems, Proceedings of the 2019 Annual Conference on Experimental and Applied Mechanics ; 2019 SEM Annual Conference and Exposition on Experimental and Applied Mechanics ; https://hal.science/hal-02443369 ; 2019 SEM Annual Conference and Exposition on Experimental and Applied Mechanics, Jun 2019, Reno, United States. ⟨10.1007/978-3-030-30098-2_7⟩, 2019
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  17. Detailansicht für Treffer 17 öffnen
    Coupled NIRT / 3D-DIC for a FEMU identification of the thermo-mechanical behavior of Zr-4 claddings under simulated Reactivity Initiated Accident
    Jailin, T ; Tardif, Nicolas ; et al.
    In: Residual Stress, Thermomechanics & Infrared Imaging and Inverse Problems, Proceedings of the 2019 Annual Conference on Experimental and Applied Mechanics ; 2019 SEM Annual Conference and Exposition on Experimental and Applied Mechanics ; https://hal.science/hal-02443369 ; 2019 SEM Annual Conference and Exposition on Experimental and Applied Mechanics, Jun 2019, Reno, United States. ⟨10.1007/978-3-030-30098-2_7⟩, 2019
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  18. Detailansicht für Treffer 18 öffnen
    Coupled NIRT / 3D-DIC for a FEMU identification of the thermo-mechanical behavior of Zr-4 claddings under simulated Reactivity Initiated Accident
    Jailin, T ; Tardif, Nicolas ; et al.
    In: Residual Stress, Thermomechanics & Infrared Imaging and Inverse Problems, Proceedings of the 2019 Annual Conference on Experimental and Applied Mechanics ; 2019 SEM Annual Conference and Exposition on Experimental and Applied Mechanics ; https://hal.science/hal-02443369 ; 2019 SEM Annual Conference and Exposition on Experimental and Applied Mechanics, Jun 2019, Reno, United States. ⟨10.1007/978-3-030-30098-2_7⟩, 2019
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  19. Detailansicht für Treffer 19 öffnen
    Coupled NIRT / 3D-DIC for a FEMU identification of the thermo-mechanical behavior of Zr-4 claddings under simulated Reactivity Initiated Accident
    Jailin, T ; Tardif, Nicolas ; et al.
    In: Residual Stress, Thermomechanics & Infrared Imaging and Inverse Problems, Proceedings of the 2019 Annual Conference on Experimental and Applied Mechanics ; 2019 SEM Annual Conference and Exposition on Experimental and Applied Mechanics ; https://hal.science/hal-02443369 ; 2019 SEM Annual Conference and Exposition on Experimental and Applied Mechanics, Jun 2019, Reno, United States. ⟨10.1007/978-3-030-30098-2_7⟩, 2019
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  20. Detailansicht für Treffer 20 öffnen
    A Predictive Process Design Kit for Three-Independent-Gate Field-Effect Transistors
    Cadareanu, Patsy ; Gore, Ganesh ; et al.
    In: IFIP Advances in Information and Communication Technology ; 27th IFIP/IEEE International Conference on Very Large Scale Integration - System on a Chip (VLSI-SoC) ; https://hal.inria.fr/hal-03476610 ; 27th IFIP/IEEE International Conference on Very Large Scale Integration - System on a Chip (VLSI-SoC), Oct 2019, Cusco, Peru. pp.307-322, ⟨10.1007/978-3-030-53273-4_14⟩, 2019
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