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In: TimesTech, 2022-11-04serialPeriodicalZugriff:
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In: IEEE Transactions on Computers, Jg. v42 (1993-12-01), Heft n12, S. 1510-1516Online academicJournalZugriff:
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In: IEEE Design & Test of Computers, Jg. v9 (1992-03-01), Heft n1, S. 72-83Online academicJournalZugriff:
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Efficient techniques in the sizing and constrained optimisation of CMOS combinational logic circuitsIn: IEE Proceedings Part E Computers and Digital Techniques, Jg. v138 (1991-05-01), Heft n3, S. 154-164academicJournalZugriff:
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In: Microwave and Optical Technology Letters, Jg. 55 (2013-05-01), Heft 5, S. 1011-1014Online academicJournalZugriff:
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In: Electronic Engineering Times, 1990-06-01, Heft n596A, S. 16-19serialPeriodicalZugriff:
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In: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Jg. v16 (1997-08-01), Heft n8, S. 930-935Online academicJournalZugriff:
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In: Electronic Design, Jg. v38 (1990-06-28), Heft n12, S. 53-55serialPeriodicalZugriff:
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In: Product News Network, 2015-09-25serialPeriodicalZugriff:
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In: Telecommunications Weekly, 2020-08-26, S. 113ZeitungsartikelZugriff: