CMOS Delay and Power Model Equations for Simultaneous Transistor and Interconnect Wire Analysis and Optimization.
In: VLSI Design, Jg. 15 (2002-11-01), Heft 3, S. 619-628
Online
academicJournal
Zugriff:
Titel: |
CMOS Delay and Power Model Equations for Simultaneous Transistor and Interconnect Wire Analysis and Optimization.
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Autor/in / Beteiligte Person: | Lee, Sangho ; Greeneich, Edwin W. |
Link: | |
Zeitschrift: | VLSI Design, Jg. 15 (2002-11-01), Heft 3, S. 619-628 |
Veröffentlichung: | 2002 |
Medientyp: | academicJournal |
ISSN: | 1065-514X (print) |
DOI: | 10.1080/1065514021000012237 |
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