An energy-efficient high-speed CMOS hybrid comparator with reduced delay time in 40-nm CMOS process.
In: Analog Integrated Circuits & Signal Processing, Jg. 89 (2016-10-01), Heft 1, S. 231-238
Online
academicJournal
Zugriff:
Titel: |
An energy-efficient high-speed CMOS hybrid comparator with reduced delay time in 40-nm CMOS process.
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Autor/in / Beteiligte Person: | Huang, Sen ; Diao, Shengxi ; Lin, Fujiang |
Link: | |
Zeitschrift: | Analog Integrated Circuits & Signal Processing, Jg. 89 (2016-10-01), Heft 1, S. 231-238 |
Veröffentlichung: | 2016 |
Medientyp: | academicJournal |
ISSN: | 0925-1030 (print) |
DOI: | 10.1007/s10470-016-0811-4 |
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