A Self-Aligned Gate-Last Process Applied to All-III–V CMOS on Si.
In: IEEE Electron Device Letters, Jg. 39 (2018-07-01), Heft 7, S. 935-938
Online
academicJournal
Zugriff:
Titel: |
A Self-Aligned Gate-Last Process Applied to All-III–V CMOS on Si.
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Autor/in / Beteiligte Person: | Jonsson, Adam ; Svensson, Johannes ; Wernersson, Lars-Erik |
Link: | |
Zeitschrift: | IEEE Electron Device Letters, Jg. 39 (2018-07-01), Heft 7, S. 935-938 |
Veröffentlichung: | 2018 |
Medientyp: | academicJournal |
ISSN: | 0741-3106 (print) |
DOI: | 10.1109/LED.2018.2837676 |
Sonstiges: |
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