A 950 MHz Clock 47.5 MHz BW 4.7 mW 67 dB SNDR Discrete Time Delta Sigma ADC Leveraging Ring Amplification and Split-Source Comparator Based Quantizer in 28 nm CMOS.
In: IEEE Journal of Solid-State Circuits, Jg. 57 (2022-07-01), Heft 7, S. 2068-2077
Online
academicJournal
Zugriff:
Titel: |
A 950 MHz Clock 47.5 MHz BW 4.7 mW 67 dB SNDR Discrete Time Delta Sigma ADC Leveraging Ring Amplification and Split-Source Comparator Based Quantizer in 28 nm CMOS.
|
---|---|
Autor/in / Beteiligte Person: | Santana, Lucas Moura ; Martens, Ewout ; Lagos, Jorge ; Hershberg, Benjamin ; Wambacq, Piet ; Craninckx, Jan |
Link: | |
Zeitschrift: | IEEE Journal of Solid-State Circuits, Jg. 57 (2022-07-01), Heft 7, S. 2068-2077 |
Veröffentlichung: | 2022 |
Medientyp: | academicJournal |
ISSN: | 0018-9200 (print) |
DOI: | 10.1109/JSSC.2022.3163819 |
Sonstiges: |
|