A 15 MHz to 600 MHz, 20 mW, 0.38 mm^2 Split-Control, Fast Coarse Locking Digital DLL in 0.13 \mum CMOS.
In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Jg. 20 (2012-03-01), Heft 3, S. 564-568
Online
academicJournal
Zugriff:
Titel: |
A 15 MHz to 600 MHz, 20 mW, 0.38 mm^2 Split-Control, Fast Coarse Locking Digital DLL in 0.13 \mum CMOS.
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Autor/in / Beteiligte Person: | Hoyos, Sebastian ; Tsang, Cheongyuen W. ; Vanderhaegen, Johan ; Chiu, Yun ; Aibara, Yasutoshi ; Khorramabadi, Haideh ; Nikolic, Borivoje |
Link: | |
Zeitschrift: | IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Jg. 20 (2012-03-01), Heft 3, S. 564-568 |
Veröffentlichung: | 2012 |
Medientyp: | academicJournal |
ISSN: | 1063-8210 (print) |
DOI: | 10.1109/TVLSI.2011.2106170 |
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