10–315-MHz Cascaded Hybrid Phase-Locked Loop for Pixel Clock Generation.
In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Jg. 21 (2013-11-01), Heft 11, S. 2080-2093
Online
academicJournal
Zugriff:
Titel: |
10–315-MHz Cascaded Hybrid Phase-Locked Loop for Pixel Clock Generation.
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Autor/in / Beteiligte Person: | Song, Minyoung ; Kwak, Young-Ho ; Ahn, Sunghoon ; Park, Hojin ; Kim, Chulwoo |
Link: | |
Zeitschrift: | IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Jg. 21 (2013-11-01), Heft 11, S. 2080-2093 |
Veröffentlichung: | 2013 |
Medientyp: | academicJournal |
ISSN: | 1063-8210 (print) |
DOI: | 10.1109/TVLSI.2012.2227068 |
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