Bias temperature instability model using dynamic defect potential for predicting CMOS aging.
In: Journal of Applied Physics, Jg. 123 (2018-06-11), Heft 22, S. N.PAG- (9S.)
Online
academicJournal
Zugriff:
This paper describes a new approach for modeling bias-temperature instability (BTI) in nanoscale transistors. The model uses non-iterative surface potential solvers enhanced with dynamic defect potential equations to enable accurate, physics-based circuit level simulations that incorporate BTI effects. Defect maps constructed from experimental data reported on high-k-metal-gate bulk complementary metal-oxide-semiconductor devices are used to parameterize the defect potential equation. By implementing the enhanced surface potential model in Verilog-A, both DC and AC BTI aging effects in combinational circuits are simulated and the results compared conventional threshold voltage shift methods for BTI modeling. [ABSTRACT FROM AUTHOR]
Titel: |
Bias temperature instability model using dynamic defect potential for predicting CMOS aging.
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Autor/in / Beteiligte Person: | Fang, Runchen ; Livingston, Ian ; Esqueda, Ivan Sanchez ; Kozicki, Michael ; Barnaby, Hugh |
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Zeitschrift: | Journal of Applied Physics, Jg. 123 (2018-06-11), Heft 22, S. N.PAG- (9S.) |
Veröffentlichung: | 2018 |
Medientyp: | academicJournal |
ISSN: | 0021-8979 (print) |
DOI: | 10.1063/1.5027856 |
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