On the Design of RNS Inter-Modulo Processing Units for the Arithmetic-Friendly Moduli Sets {2 n + k , 2 n − 1, 2 n +1 − 1}.
In: Computer Journal, Jg. 62 (2019-02-01), Heft 2, S. 292-300
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Zugriff:
Inter-modulo arithmetic operations, such as reverse conversion and scaling, are important but difficult operations in the RNS domain. This paper proposes efficient arithmetic units to perform this hard class of RNS operations for a new family of augmented three-moduli sets { 2 n + k, 2 n − 1, 2 n + 1 − 1 } (0 ≤ k ≤ n) . Experimental results for 65 nm CMOS technology show that the proposed reverse converter reduces the delay by about (17.6 − 33.4) % in comparison with the state of the art. Moreover, this work presents the first architecture of a scaler dedicated for this augmented three-moduli sets. [ABSTRACT FROM AUTHOR]
Titel: |
On the Design of RNS Inter-Modulo Processing Units for the Arithmetic-Friendly Moduli Sets {2 n + k , 2 n − 1, 2 n +1 − 1}.
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Autor/in / Beteiligte Person: | Hiasat, Ahmad ; Sousa, Leonel |
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Zeitschrift: | Computer Journal, Jg. 62 (2019-02-01), Heft 2, S. 292-300 |
Veröffentlichung: | 2019 |
Medientyp: | academicJournal |
ISSN: | 0010-4620 (print) |
DOI: | 10.1093/comjnl/bxy119 |
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