Design of CMOS three-stage amplifiers for near-to-minimum settling-time.
In: Microelectronics Journal, Jg. 107 (2021), S. N.PAG
academicJournal
Zugriff:
In this paper, we provide a new procedure that allows to design a generic three-stage amplifier from settling-time specifications. The procedure analyze the settling-time of pure two- or three-pole amplifiers (i.e., with no zeros) and extends the results to a generic amplifier that includes one or two zeros even placed in the right-half plane. The validity of the proposed approach is demonstrated through a design example of a three-stage CMOS amplifier suitable for switched-capacitor applications. [ABSTRACT FROM AUTHOR]
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Design of CMOS three-stage amplifiers for near-to-minimum settling-time.
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Autor/in / Beteiligte Person: | Giustolisi, Gianluca ; Palumbo, Gaetano |
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Zeitschrift: | Microelectronics Journal, Jg. 107 (2021), S. N.PAG |
Veröffentlichung: | 2021 |
Medientyp: | academicJournal |
ISSN: | 0026-2692 (print) |
DOI: | 10.1016/j.mejo.2020.104939 |
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