CMOS realization of electronically tunable VDCC based single-input-dual-output filter.

This paper introduces a CMOS implementation of filter application based on single Voltage Differencing Current Conveyor (VDCC). The filter employs a single VDCC, one floating capacitor and three grounded passive components. The designed filter can simultaneously implement the band-pass and high-pass filtering responses. By means of the trans-conductance gain of the VDCC, the angular frequency and quality factor of the filter can be dynamically modified. Furthermore, avoid conflicting with the natural frequency, the quality factor can also be tuned. Layout, pre and post layout simulations are carried out for the circuits, the proposed filter which occupies 68 μ m × 23 μ m area excluding the area of the passive components, using 0.18 μ m AMS CMOS process parameters in Cadence environment. The proposed VDCC structure can utilize additional high-impedance z-copy terminal. The natural frequency of the filter is designed as 100 MHz which is suitable for the RF applications. Post-layout simulations with noise, THD, PVT, and Monte Carlo analyzes are conducted with the Spectre simulator to assess the feasibility of the developed structures. The findings of the simulations are found to be closely in consistent with the theoretical research. [ABSTRACT FROM AUTHOR]