An 8.25b-ENOB 100kSps 290fJ-FoM asynchronous SAR capacitance to digital converter.

This paper presents a low-power asynchronous capacitance to digital converter achieving 8.25-bit Effective Number of Bits (ENOB), and 290-fJ/conversion.step Figure of Merit (FoM) at 100 kHz sampling per cycle and 1.4 V supply voltage. The asynchronous mechanism enables the converter to generate an internal clock signal itself and therefore reduces the design complexity and power-consumption. Moreover, a differential architecture relying on the sole capacitive sensor guarantees that performance of the converter is not affected by fluctuations of the input capacitance and of the comparator common-mode voltage during the conversion. A prototype being fabricated in standard 0.18 μm CMOS technology occupies 0.13 mm2 area, though, this can be reduced if capacitor arrays cancelling the initial capacitance of the sensor at the atmospheric pressure are alleviated. Measurement result fits with the real capacitive sensor characteristic. [ABSTRACT FROM AUTHOR]