Modeling Silicon Cylindrical CMOS Nanotransistors with a Fully Enclosed Variable-Radius Gate.

A new silicon CMOS nanotransistor with a cylindrical geometry of a fully enclosed variable-radius gate is discussed. A 2-D analytical model of the potential distribution and models of direct and subthreshold currents of a transistor with a truncated cone-shaped operating region based on it are developed. Changing the geometry of the transistor from the usual cylindrical shape improves the electrical-physical characteristics and allows us to compensate the limitations resulting from scaling. Numerical studies of conical prototypes demonstrate improved electrostatic performance at an optimized radius ratio of 0.83 compared to a conventional cylindrical structure in the control voltage range from 0 to 0.6 V. The conical structure features a higher transistor current, maximum current ratio Ion/Ioff, low leakage current, and the slope of the subthreshold characteristic close to the theoretical limit. Thus, a conical architecture with an optimized radius ratio can replace a cylindrical structure for high-speed and low-voltage applications. [ABSTRACT FROM AUTHOR]