Nanopore‐application CMOS potentiostat design with input parasitic compensation.
In: Electronics Letters (Wiley-Blackwell), Jg. 50 (2014-04-01), Heft 8, S. 578-579
Online
academicJournal
Zugriff:
Titel: |
Nanopore‐application CMOS potentiostat design with input parasitic compensation.
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Autor/in / Beteiligte Person: | Kim, Jungsuk ; Dunbar, W.B. |
Link: | |
Zeitschrift: | Electronics Letters (Wiley-Blackwell), Jg. 50 (2014-04-01), Heft 8, S. 578-579 |
Veröffentlichung: | 2014 |
Medientyp: | academicJournal |
ISSN: | 0013-5194 (print) |
DOI: | 10.1049/el.2014.0049 |
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