ESD Implantations for On-Chip ESD Protection With Layout Consideration in 0.18-μm Salicided CMOS Technology.
In: IEEE Transactions on Semiconductor Manufacturing, Jg. 18 (2005-05-01), Heft 2, S. 328-337
Online
academicJournal
Zugriff:
Titel: |
ESD Implantations for On-Chip ESD Protection With Layout Consideration in 0.18-μm Salicided CMOS Technology.
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Autor/in / Beteiligte Person: | Ker, Ming-Dou ; Chuang, Che-Hao ; Lo, Wen-Yu |
Link: | |
Zeitschrift: | IEEE Transactions on Semiconductor Manufacturing, Jg. 18 (2005-05-01), Heft 2, S. 328-337 |
Veröffentlichung: | 2005 |
Medientyp: | academicJournal |
ISSN: | 0894-6507 (print) |
DOI: | 10.1109/TSM.2005.845100 |
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