A New Approach for Dimensional Optimization of Inverters in 6T-Static Random-Access Memory Cell Based on Silicon Nanowire Transistor.
In: Journal of nanoscience and nanotechnology, Jg. 17 (2017-02-01), Heft 2, S. 1061-067
academicJournal
Zugriff:
This study explores dimensional optimization at different high logic-level voltages for six silicon nanowire transistor (SiNWT)-based static random-access memory (SRAM) cell. This study is the first to demonstrate diameter and length of nanowires with different logic voltage level (V dd optimizations of nanoscale SiNWT-based SRAM cell. Noise margins and inflection voltage of butterfly characteristics are used as limiting factors in this optimization. Results indicate that optimization depends on nanowire dimensions and V dd. The increase in V dd from 1 V to 3 V tends to decrease the dimensions of the optimized nanowires but increases the current and power. SRAM using nanowire transistors must use V dd of 2 or 2.5 V to produce SRAM with lower dimensions, inflection currents, and power consumption.
Titel: |
A New Approach for Dimensional Optimization of Inverters in 6T-Static Random-Access Memory Cell Based on Silicon Nanowire Transistor.
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Autor/in / Beteiligte Person: | Hashim, Y |
Zeitschrift: | Journal of nanoscience and nanotechnology, Jg. 17 (2017-02-01), Heft 2, S. 1061-067 |
Veröffentlichung: | Stevenson Ranch, CA : American Scientific Publishers, 2001-2021, 2017 |
Medientyp: | academicJournal |
ISSN: | 1533-4880 (print) |
DOI: | 10.1166/jnn.2017.12608 |
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