Silicon-van der Waals heterointegration for CMOS-compatible logic-in-memory design.
In: Science advances, Jg. 9 (2023-12-08), Heft 49, S. eadk1597
Online
academicJournal
Zugriff:
Silicon CMOS-based computing-in-memory encounters design and power challenges, especially in logic-in-memory scenarios requiring nonvolatility and reconfigurability. Here, we report a universal design for nonvolatile reconfigurable devices featuring a 2D/3D heterointegrated configuration. By leveraging the photo-controlled charge trapping/detrapping process and the partially top-gated energy band landscape, the van der Waals heterostacking achieves polarity storage and logic reconfigurable characteristics, respectively. Precise polarity tunability, logic nonvolatility, robustness against high temperature (at 85°C), and near-ideal subthreshold swing (80 mV dec -1 ) can be done. A comprehensive investigation of dynamic charge fluctuations provides a holistic understanding of the origins of nonvolatile reconfigurability (a trap level of 10 13 cm -2 eV -1 ). Furthermore, we cascade such nonvolatile reconfigurable units into a monolithic circuit layer to demonstrate logic-in-memory computing possibilities, such as high-gain (65 at V dd = 0.5 V) logic gates. This work provides an innovative 3D heterointegration prototype for future computing-in-memory hardware.
Titel: |
Silicon-van der Waals heterointegration for CMOS-compatible logic-in-memory design.
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Autor/in / Beteiligte Person: | Lee, MP ; Gao, C ; Tsai, MY ; Lin, CY ; Yang, FS ; Sung, HY ; Zhang, C ; Li, W ; Li, J ; Zhang, J ; Watanabe, K ; Taniguchi, T ; Ueno, K ; Tsukagoshi, K ; Ho, CH ; Chu, J ; Chiu, PW ; Li, M ; Wu, WW ; Lin, YF |
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Zeitschrift: | Science advances, Jg. 9 (2023-12-08), Heft 49, S. eadk1597 |
Veröffentlichung: | Washington, DC : American Association for the Advancement of Science, [2015]-, 2023 |
Medientyp: | academicJournal |
ISSN: | 2375-2548 (electronic) |
DOI: | 10.1126/sciadv.adk1597 |
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