Short-range Internet of Things (IoT) sensor nodes operating at 2.4 GHz must provide ubiquitous wireless sensor networks (WSNs) with energy-efficient, wide-range output power (POUT). They must also be fully integrated on a single chip for wireless body area networks (WBANs) and wireless personal area networks (WPANs) using low-power Bluetooth (BLE) and Zigbee standards. The proposed fully integrated transmitter (TX) utilizes a digitally controllable current-mode class-D (CMCD) power amplifier (PA) with a second harmonic distortion (HD2) suppression to reduce VCO pulling in an integrated system while meeting harmonic limit regulations. The CMCD PA is divided into 7-bit slices that can be reconfigured between differential and single-ended topologies. Duty cycle distortion compensation is performed for HD2 suppression, and an HD2 rejection filter and a modified C-L-C low-pass filter (LPF) reduce HD2 further. Implemented in a 28 nm CMOS process, the TX achieves a wide POUT range of from 12.1 to −31 dBm and provides a maximum efficiency of 39.8% while consuming 41.1 mW at 12.1 dBm POUT. The calibrated HD2 level is −82.2 dBc at 9.93 dBm POUT, resulting in a transmitter figure of merit (TX_FoM) of −97.52 dB. Higher-order harmonic levels remain below −41.2 dBm even at 12.1 dBm POUT, meeting regulatory requirements.
Keywords: bluetooth low energy (BLE); class-D power amplifier (PA); complementary metal–oxide–semiconductor (CMOS); current-mode; second harmonic distortion (HD2); internet of things (IoT); transmitter (TX); power efficiency; wireless sensor network (WSN); Zigbee
A wireless sensor network (WSN) consists of a large number of infrastructure-less wireless sensors deployed in an ad hoc manner, where each sensor node is used to monitor system, physical, or environmental conditions in a specific area [[
The sensor nodes support both wireless personal area networks (WPANs) for long-range applications, such as smart homes [[
The most vital and energy-hungry part is the power amplifier (PA), which consumes more than 50% of the available power in the IoT sensor node [[
PAs also generate electromagnetic waves at unintended frequencies. Strong harmonic spurious emissions can potentially contaminate the out-of-band spectrum, causing receivers (RXs) operating at the same harmonic frequencies to desensitize. As a sensor node operating in the industrial, scientific, and medical (ISM) band, spurious emissions are categorized as any electromagnetic emissions that occur at frequencies that are not intentionally emitted, especially for electronics that intentionally emit one or more frequencies. Therefore, all electronics are required to be tested to ensure that they do not emit electromagnetic waves of excessive intensity at all frequencies except those at which they are intentionally emitted, which is known as electromagnetic compatibility (EMC) testing as shown in Figure 2a. Furthermore, the TX must meet more stringent harmonic levels corresponding to conducted power of <−41.2 dBm as shown in Figure 2b. For example, the second harmonic (HD2) of a 2.4 GHz TX is located at the N79 band of a 5 G NR [[
This paper introduces a TX with a digitally controllable current-mode Class-D (CMCD) PA, second-harmonic distortion (HD2) super-compression, and passive filters for harmonic component reduction. It employs digitally controlled multi-slice switches and dual-mode operation in differential and single-ended PA configurations to handle a wide range of output power for a variety of ubiquitous IoT applications. It also reduces HD2 distortion with duty-cycle compensation, an on-die HD2 rejection filter, and an externally modified CLC low-pass filter (LPF). This article is organized in the following manner. Section 2 presents an overview of class-D PAs. Section 3 describes the overall block diagram of the proposed TX and the wideband CMCD PA with harmonic suppression technique. Section 4 discusses the experimental results of the proposed TX obtained on the integrated circuit fabricated in 28 nm CMOS technology. Finally, the main contributions are summarized in Section 5.
Switched-mode PAs have the characteristic that the product of the voltage and current waveforms applied to the transistor becomes zero, so the power consumed by the transistor becomes zero, showing a theoretical efficiency of 100%. However, the theoretical high efficiency cannot be obtained due to the effect of parasitic components present in the transistor, and the loss due to parasitic components increases as the operating frequency increases, which limits its use in high-frequency bands. Class-E/F PAs have received much attention as amplifiers for wireless power transmission systems due to their ease of use, heat dissipation, and simple structure. However, compared to other PAs, they are less efficient at utilizing high power and require switch elements with high breakdown voltages due to their high drain-source peak voltages [[
The class-D PAs are categorized as voltage-controlled and current-controlled. As shown in Figure 3a, a voltage-mode class-D (VMCD) PA operates two transistors by switching each transistor on and off with a 180° phase difference, which causes the drain voltage waveform to be a square wave, and only the desired frequency components are delivered to the load through a series resonant circuit connected to the load. The series filter has a resonant frequency that is set to the center frequency of the output signal. The voltage across the transistor is a square wave and the transistor current will be a half-wave rectified sine wave, which is theoretically 100% efficient. However, the efficiency of the transistor can be reduced if there is some parasitic drain-source capacitance (C
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where V
Figure 4 shows the proposed TX architecture. Gaussian minimum shift keying (GMSK) based on two-point modulated data of a phase-locked loop is used for the differential inputs (IN/INB) of the TX. The HD2 suppression (HD2S) block is used to reduce HD2, which can mitigate VCO pulling and meet out-of-band spurious emissions, including second and third harmonic distortion (HD3) magnitudes below absolute −41 dBm. The following CMCD PA provides a wide range of output power with digital control signals of SE_EN<6:0> and DIFF_EN<6:0>. The CMCD PA is connected to a 3:2 transformer (XFMR) to provide impedance matching and a differential signal as a single-ended signal for driving an external antenna. The XFMR also includes an LC parallel HD2 rejection filter to further reject HD2. Two low-dropout voltage regulators are used to provide stable supply voltages. The first LDO output is assigned for thin oxide transistors that are used in all TX blocks except the CMCD PA block. The second LDO output is connected to the XFMR center tap to provide the power to the CMCD PA arrays using nMOSFET transistors and isolate other circuitries from high-power PA. Two low-dropout voltage regulators are used to provide a stable supply voltage, and their outputs are 1.0 V. A typical electrostatic discharge (ESD) protection circuit with double diodes is added at the PAD. An external CLC π-type low-pass filter is added right next to the external PAD to reduce harmonics additionally.
Figure 5a shows a wide-range CMCD PA. The PA consists of two thick oxide nMOSFETs to withstand the high output power. The C
Figure 6a shows the transformer (XFMR) and HD2 rejection filter inductor block used for the proposed CMCD PA. The XFMR implements the main inductor and connection crossings with two top metal lines while meeting the electrical migration rules. A ring structure is added around the XFRM to reduce unwanted second-harmonic coupling to the nearby circuits including the HD2 rejection filter inductor and the VCO inductor. A 3D electromagnetic simulation is performed to obtain the extracted values of the XFMR and inductor, and the corresponding schematics and their values are shown in Figure 6b. The larger the inductance, the more favorable it is for increasing the Q-factor of the resonant circuits. The switched capacitor (C
The HD2 rejection filter is implemented as an LC band-stop filter or notch filter as shown in Figure 5a. The parallel LC components of L
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The embedded low-loss switch scheme [[
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An impedance matching is achieved by using the 3:2 XFMR (n = 2/3) and the HD2 rejection filter between differential high-output impedance of the PA and single-ended low impedance of an antenna in the TX mode. The XFMR changes impedance of CMCD PA by multiplying n
The proposed CMCD PA has two switched capacitors. One is the primary resonant capacitor of the XFMR, and the other is for the HD2 rejection filter. Since the CMCD PA is a differential circuit, the switched capacitors must also be differential, which uses two 2× capacitors in series compared to a single-ended structure. For the HD2 rejection filter, since it is a single-ended filter, a single-ended switch capacitor structure can be applied. However, a differential structure should also be used for the HD2 rejection filter because, in a single-ended structure, the switch thick oxide nMOSFETs are directly connected to the PAD, making them vulnerable to ESD damage as shown in Figure 8a. In the differential configuration, there is no direct current path from the PAD. The differential configuration uses the triple-well that helps float the device's body voltage to prevent junction failures due to potentially large swings across all nodes of the switch as shown in Figure 8b. Similarly, the gate, drain, and source nodes are also floated while being DC-biased through large resistors. A large resistor of 20 kΩ is chosen to minimize the insertion loss of the switch. When the switch is on, the source and drain node DC voltages are pulled to GND. When the switch is off, the source and drain node DC voltages are pulled to VDD. This prevents the junction from being biased forward due to the swing seen on the other port after the switch is turned on, potentially degrading linearity or gain. The switch transistor size is 20 μm/150 nm.
Differential PA topologies are commonly used to suppress HD2 emissions, which can violate spurious emission limits in wireless standards. However, its effectiveness is limited by device mismatch and asymmetry. The HD2 is caused by the input data duty-cycle imbalance, so the proposed TX employs a duty-cycle correction circuit (DCC) before driving the CMCD PA. Figure 9a shows the block diagram of the successive approximation register (SAR)-DCC circuit, which consists of a duty-cycle distortion corrector (DCDC), a duty-cycle detector (DCD), and a SAR logic controller. The DCD essentially consists of an analog integrator and a comparator. The integrator is a fully differential charge pump with a common-mode feedback circuit, and the fully differential dynamic comparator is based on two cross-coupled differential pairs with switched current sources loaded with a CMOS latch. The output of the comparator is given to the SAR logic controller that adopts the binary search algorithm and adjusts load capacitances in the DCDC to correct the input duty cycle by 50%. The duty-cycle error correction loop is continuously running to compensate for voltage and temperature drift. A 10 MHz clock is used to run the error detection and correction logic.
Figure 9b shows the digitally controlled DCDC circuit. The first stage of the DCDC, an AC-coupled resistive feedback inverter, compensates for the duty-cycle error to some extent on its own. This is done by storing the average value of the input in an AC capacitor. Change the common-mode voltage at the input of the first-stage inverter. The DCDC calibration is performed down to 1.5 ns with a resolution of up to ±45 ns in the time domain by the digital control words P<5:0> and N<5:0>, which independently adjusts the pull-up and pull-down resistors of the delay device. This corresponds to a correction operation of ±32 degrees in the phase domain, with a resolution of approximately 0.5 degrees at a data rate of 2 Mb/s.
An external C-L-C filter consisting of a capacitor-inductor-capacitor in a π configuration creates a low-pass filter (LPF) for harmonics suppression as shown in Figure 10a. The input capacitor (C
Microstrip inductance of 600 pH is added between C
Figure 11 shows a micrograph of the proposed TX implemented in a 1P8M 28-nm CMOS process. It includes the HD2 suppression block, the CMCD PA, the XFMR, the HD2 rejection filter, the ESD diodes on the die, and input/output PADs. The die area is 0.385 mm
Figure 12 shows the hardware test setup for the fabricated transmitter chip. The chip is embedded on a device under test (DUT) board using a chip-on-board package on a 1.6 mm thick FR4 substrate. The unmodulated and modulated input signals of Gaussian frequency-shift keying (GFSK) and offset quadrature phase-shift keying (O-QPSK) are generated by a PHY transmitter and a modulation device with a two-point modulation synthesizer. The control registers of the DUT and the modulator are configured by a Xilinx Spartan-6 mounted on an integrated FPGA board (Opal Kelly Inc., Portland, OR, USA). The FPGA communicates with the PC via a USB 3.0 module. A signal generator E4433B (Keysight Technologies, Colorado Springs, CO, USA) provides a 10 MHz system clock signal to the DUT and modulator. The output spectrum is analyzed or measured with a spectrum analyzer E4440A (Keysight Technologies, Colorado Springs, CO, USA).
The maximum output power of the differential CMCD PA is 12.13 dBm for unmodulated data as shown in Figure 13a. In addition, the PA can be digitally tuned between −24.9 and +12.1 dBm by changing the number of slices from 1 to 127 as shown in Figure 13b. The proposed PA also offers a single-ended configuration with a minimum output power of −30.9 dBm for unmodulated data as shown in Figure 13c. Figure 13d shows digitally controllable output powers from −30.9 to 9.2 dBm by varying the number of slices from 1 to 127 for the single-ended configuration. Thus, different output-power levels can be achieved by mixing differential and single-ended configurations.
Figure 14 shows the TX harmonic-suppression performance at the maximum free frequency channel of 2.48 GHz with and without HD2 suppression using duty-cycle distortion correction. Under the +9.68 dBm output-power condition without duty-cycle correction, the harmonic level of HD2 is −50.2 dBm and HD3 exhibits −56.9 dBm as shown in Figure 13a. The harmonic levels can meet the regulatory limit of −41.2 dBm with the help of the HD2 rejection filter and modified C-L-C LPF filter. After enabling duty-cycle correction for HD2 suppression, the fundamental output power is +9.93 dBm, the HD2 level decreases to −70.1 dBm, and the HD3 level achieves −57.4 dBm as shown in Figure 13b. Thus, the HD2 suppression function block is found to improve the HD2 level by 20.2 dB.
Figure 15a shows the measured power breakdown of the proposed TX. Under the +12.1 dBm output-power condition at 2.48 GHz, the TX consumes 41 mW of DC power (P
Figure 16 shows the TX spectrums of the 2 Mb/s data rate Gaussian frequency-shift keying (GFSK) modulation for the BLE mode and of the 256 kb/s data rate offset quadrature phase shift keying (O-QPSK) modulation for Zigbee mode. The modulated output spectrums are measured with the maximum P
The performance of this work is summarized and benchmarked against state-of-the-art TXs operating at the 2.4 GHz ISM band for IoT applications [[
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The high-efficiency wide-range transmitter using the digitally controlled CMOS current-mode Class-D switching PA is demonstrated in a 28 nm CMOS technology with an area of 0.39 mm
Graph: Figure 1 WBAN and WPAN for wireless sensor networks.
Graph: Figure 2 (a) electromagnetic compatibility and (b) harmonic spurious emission regulation of BLE and (c) oscillator pulling due to high power outputs of the PA.
Graph: Figure 3 (a) Voltage mode class-D PA (VMCD) and (b) current mode class D PA (CMCD).
Graph: Figure 4 Proposed transmitter architecture block diagram.
Graph: Figure 5 (a) Wide-range CMCD PA, (b) AND gate, and (c) differential and (d) single-ended CMCD.
Graph: Figure 6 (a) XFMR and inductor of HD2 rejection filter and (b) their equivalent circuit.
Graph: Figure 7 Embedded low-loss TX switch for RX operation mode.
Graph: Figure 8 (a) Single-ended and differential switched-capacitor scheme for HD2 rejection filter and (b) differential switched-capacitor configuration using triple-well.
DIAGRAM: Figure 9 (a) HD2 suppression block diagram and (b) digitally controlled DCDC circuit.
Graph: Figure 10 (a) C-L-C LPF, (b) modified C-L-C having microstrip inductance LPF, and (c) their magnitude frequency response.
Graph: Figure 11 Microphotograph of the proposed transmitter.
Graph: Figure 12 Measurement setup used for the proposed transmitter characterization.
Graph: Figure 13 (a) The measured maximum output power of the differential CMCD PA, (b) its output power as a function of the number of slices, (c) the measured minimum output power of the single-ended CMCD PA, and (d) its output power as a function of the number of slices.
Graph: Figure 14 Measured TX typical harmonic: (a) without and (b) with HD2 suppression.
Graph: Figure 15 (a) Breakdown of measured TX power consumption and (b) DC power (PDC) and efficiency as a function of the number of slices.
Graph: Figure 16 Measured TX spectrum (a) at 2 Mb/s for BLE5.0 and (b) at 256 kb/s for Zigbee.
Table 1 Performance summary of the proposed TX and comparisons to the state-of-the arts.
This Work [ [ [ [ [ [ [ [ Technology (nm) 28 40 55 40 55 55 65 55 28 Supply 1.0 1.1 1.2 1.1 3 3.3 0.6 3.0 1 PA Topology Class-D Class-E Class-AB Class-D Class-D Class-D Class-E/F2 Class-D Class-E Area (mm2) 0.39 0.48 2.2 ** 0.7 0.53 N/A 0.85 ** 2.9 ** 0.112 *** TX max POUT (dBm) 12.1 0 8 4 10.05 0 0 0 24.1 TX min POUT (dBm) −31 −10 N/A −10 −23 −20 −6 N/A 5 HD2 @ POUT (dBc) −82.2 @ +9.93 −41.3 @ −3 −58 @ +8 −52 @ 0 −45.6 @ +1.6 −54 @ 0 −58 @ 0 −50.07 @ 0 N/A HD3 @ POUT (dBc) −67.3 @ +9.93 −54.2 @ −3 −64 @ +8 −30 @ 0 −50.6 @ +1.6 −52 @ 0 −64 @ 0 −47.08 @ 0 N/A Max. PDC @ POUT (mW) 41.1 @ +12.1 4.85 @ 0 79.8 @ +8 N/A 18 @ +10 10.1 @ 0 5.4 @ 0 6 @ 0 N/A Max. Efficiency @ POUT (%) 40.6 @ +12.1 20.6 @ 0 7.9 @ +8 N/A 55.6 @ +10 9.9 @ 0 18.5 @ 0 16.7 @ 0 N/A Max. PAE @ POUT (%) 37.9 @ +11.9 N/A N/A N/A N/A N/A N/A N/A 50 @ 24.1 PDC @ POUT (mW) 29.4 @ +9.93 3.22 @ −3 79.8 @ +8 4.5 @ 0 3.9 @ +1.6 10.1 @ 0 5.4 @ 0 6 @ 0 N/A Efficiency @ POUT (%) 33 @ +9.93 15.6 @ −3 7.9 @ +8 22.2 @ 0 37.1 @ +1.6 9.9 @ 0 18.5 @ 0 16.7 @ 0 N/A PAE @ POUT (%) 32.1 @ +9.93 N/A N/A N/A N/A N/A N/A N/A N/A TX_FoM @ POUT (dB) −97.52 @ +9.93 −66.52 @ −3 −68.99 @ −3 −75.47 @ 0 −69.69 @ +1.6 −73.96 @ 0 −80.68 @ 0 −72.68 @ 0 N/A
Not applicable.
Not applicable.
Data are contained within the article.
The author declares no conflicts of interest. The funders had no role in the design of the study; in the collection, analyses, or interpretation of data; in the writing of the manuscript; or in the decision to publish the results.
By Nam-Seog Kim
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