Single-Photon Avalanche Diode theory, simulation, and high performance CMOS integration

This thesis explores Single-Photon Avalanche Diodes (SPADs), which are solid-state devices for photon timing and counting, and concentrates on SPADs integrated in nano-scale CMOS. The thesis focuses on: the search for new theory regarding Geiger-mode operation; proving the utility of calibrated Technology Computer- Aided Design (TCAD) tools for accurately simulating SPADs for the first time; the investigation of how manufacture influences device operation; and the integration of high performance SPADs into CMOS which rival discrete devices. The accepted theories of SPAD operation are revisited and it is discovered that previously neglected minority carriers have many significant roles such as determining: after-pulsing, Dark Count Rate (DCR), bipolar “SPAD latch-up,” nonequilibrium DCR, and “quenching”. The “quenching” process is revisited and it is concluded that it is the “probability time” of ≈100-200ps, and not the previously thought latching current that is important. SPADs are also found to have transient negative differential resistance. The new theories of SPADs are also supported by steady-state 1D, 2D and 3D TCAD simulations as well as novel transient simulations and videos. It is demonstrated as possible to simulate DCR, Photon Detection Efficiency (PDE), guard ring performance, breakdown voltage, breakdown voltage variation, “quenching,” and transient operation of SPADs with great accuracy. The manufacture of SPADs is studied focusing on the operation and optimisation of guard rings and it is found that ion implantation induced asymmetry from the tilt and rotation/twist is critical. Where symmetric, guard rings fail first along the directions due to enhanced mobility. Process integration rules are outlined for obtaining high performance SPADs in CMOS while maintaining compatibility with transistors. The minimisation of tunnelling with lightly-doped junctions and the reduction of ion implantation induced defects by additional annealing are found essential for achieving low DCR. The thesis demonstrates that it is possible to realise high performance SPADs in CMOS through the innovation of a “Deep SPAD” which achieves record PDE of ≈72% at 560nm with >40% PDE from 410-760nm, combined with 18Hz DCR,