Etching Process Development for SiC CMOS

Silicon Carbide (SiC) is an exciting material that is growing in popularity for having qualities that make it a helpful semiconductor in extreme environments where silicon devices fail. The development of a SiC CMOS is in its infancy. There are many improvements that need to be made to develop this technology further. Photolithography is the most significant bottleneck in the etching process; it was studied and improved upon. Etching SiC can be a challenge with its reinforced crystal structure. Chlorine-based inductively coupled plasma (ICP) etching of intrinsic SiC and doped SiC, SiO2, and Silicon has been studied. A baseline chlorine gas recipe containing Cl2 and BCl3 was studied and characterized. The average SiC etch rate of this recipe was found to be 1330 Å/min. The Cl2 concentration was then varied to over five total experimental recipes. The results show that Cl-based gas produces little change in etch rates between intrinsic SiC and doped SiC except for the recipe containing 66% Cl2. This recipe provided etch rates that were proportional to doping concentration but independent of the dopant species. These results also showed a high critical dimension bias due to sidewall passivation. Buffered oxide etching (BOE) was conducted on SiO2 for the purposed of etching field oxide, gate oxide, and hardmasks. The studies of BOE were inconsistent with the results found in the literature. Instead, an ICP method and a liftoff method was used on SiO2 as an alternative. Results from this study found that the desired SiO2 etching can be achieved without the use of BOE, which can be hazardous. The ICP etch rate of SiO2 was 1006 Å/min. Both ICP and liftoff had higher quality pattern transfer than BOE. The future works of these results have also been described.