Low-Power Multiplierless DCT Architecture Using Image Data Correlation.
In: IEEE Transactions on Consumer Electronics, Jg. 50 (2004-02-01), Heft 1, S. 262-267
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Zugriff:
Low-power design is one of the most important challenges to maximize battery life in portable devices and to save the energy during system operation. In this paper, we propose a low-power DCT (Discrete Cosine Transform) architecture using a modified multiplierless CORDIC (Coordinate Rotation Digital Computer) arithmetic. The switching power consumption is reduced during DCT: the proposed architecture does not perform arithmetic operations of unnecessary bits during the CORDIC calculations. The experiment results show that we can reduce up to 26.1% power dissipation without compromise of the final DCT results. Also, the speed of the proposed architecture is increased about 10%. The proposed low-power DCT architecture can be applied to consumer electronics and portable multimedia systems requiring high throughput and low-power. [ABSTRACT FROM AUTHOR]
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Low-Power Multiplierless DCT Architecture Using Image Data Correlation.
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Zeitschrift: | IEEE Transactions on Consumer Electronics, Jg. 50 (2004-02-01), Heft 1, S. 262-267 |
Veröffentlichung: | 2004 |
Medientyp: | academicJournal |
ISSN: | 0098-3063 (print) |
DOI: | 10.1109/TCE.2004.1277872 |
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