高性能分段线性补偿CMOS带隙基准电压源设计. (Chinese)
In: Electronic Components & Materials, Jg. 37 (2018-03-01), Heft 3, S. 73-77
academicJournal
Zugriff:
A CMOS bandgap reference with segmented linear compensation was designed. The circuit was based on the traditional bandgap reference source. A positive temperature coefficient current and a negative temperature coefficient current were generated by using a MOS transistor instead of a bipolar transistor. These two currents were summed up to the load resistance,and the compensation circuit that was added to the whole circuit was adopted to achieve a high precision reference output voltage. A negative temperature coefficient current was added to the circuit when the circuit was in the period of low temperature, similarly, a part of current was extracted by the compensation circuit when the circuit was in the period of high temperature. Base on 0.5 μm CMOS process, the circuit was simulated with Cadence Spectre. Simulation results show that the output voltage is 1.255 V when the supply voltage is 5 V, the temperature drift coefficient is 1.029×10 -6 /℃ in the temperature range of -40-125 ℃. The power supply rejection ratio (PSRR) is lower than -75 dB at low frequency. [ABSTRACT FROM AUTHOR]
计了一种具有分段线性补偿的 CMOS带隙基准电压源。该电路基于传统带隙基准源,利用 MOS晶体管代替双极型晶体管产生正温度系数电流和负温度系数电流,将这两种具有相反温度系数的电流以适当的权重相加到负载电阻,并加入分段补偿电路,在低温阶段,加入一段负温度系数的电流,在高温阶段,抽取部分总电流,从而得到高精度的基准输出电压。在 0.5 μm CMOS工艺下,使用Cadence Spectre对电路进行仿真,仿真结果表明,在供电电压为 5 V 时,基准输出电压为 1.255 V,在-40~125 ℃范围内,带隙基准源的温漂系数为1.029×10 -6 /℃,低频时的电源抑制比(PSRR)低于-75 d B。 [ABSTRACT FROM AUTHOR]
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Titel: |
高性能分段线性补偿CMOS带隙基准电压源设计. (Chinese)
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Autor/in / Beteiligte Person: | 邓庭 ; 曾以成 ; 夏俊雅 ; 崔晶晶 |
Zeitschrift: | Electronic Components & Materials, Jg. 37 (2018-03-01), Heft 3, S. 73-77 |
Veröffentlichung: | 2018 |
Medientyp: | academicJournal |
ISSN: | 1001-2028 (print) |
DOI: | 10.14106/j.cnki.1001-2028.2018.03.014 |
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