An Accurate Low-Power Power-on-Reset Circuit in 55-nm CMOS Technology.
In: IEEE Transactions on Circuits & Systems. Part II: Express Briefs, Jg. 69 (2022-08-01), Heft 8, S. 3361-3365
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Zugriff:
In this brief, an accurate low-power power-on-reset circuit is proposed. In order to get an accurate trip-voltage with little overhead, a low-power architecture based on current reference and current comparator is proposed. The reference current in the proposed power-on-reset circuit is mainly provided by the sub-threshold current of several native NMOS transistors, and a stable hysteresis window can be obtained by adjusting the number of enabled native NMOS transistors. Measurement results based on 55nm CMOS process show that the proposed power-on-reset circuit consumes only 32nW at the supply voltage of 0.5V. The measured power-on-reset trip-voltage is 0.45V with a temperature coefficient of $227~\mu \text{V}/^{\circ }\text{C}$. Since the proposed power-on reset circuit consists of only 10 transistors, the area of the proposed power-on-reset circuit is as low as $67.5~\mu \text{m}^{2}$. [ABSTRACT FROM AUTHOR]
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Titel: |
An Accurate Low-Power Power-on-Reset Circuit in 55-nm CMOS Technology.
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Autor/in / Beteiligte Person: | You, Heng ; Yuan, Jia ; Yu, Zenghui ; Qiao, Shushan |
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Zeitschrift: | IEEE Transactions on Circuits & Systems. Part II: Express Briefs, Jg. 69 (2022-08-01), Heft 8, S. 3361-3365 |
Veröffentlichung: | 2022 |
Medientyp: | academicJournal |
ISSN: | 1549-7747 (print) |
DOI: | 10.1109/TCSII.2022.3164454 |
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