Design of high-speed low power CMOS operational amplifier utilizing 0.18-µm technology for ADC applications.
In: AIP Conference Proceedings; 2023, Vol. 2579 Issue 1, p1-9, 9p; Jg. 2579 (2023-09-20) 1, S. 1-9
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Zugriff:
This paper presents a design of high-speed low power CMOS operational amplifier utilizing 0.18-µm technology for ADC applications. A folded cascode with PMOS configuration is chosen as a topology for the op-amp design which provides high-speed structure and more stable configuration compare to the other topologies. High-swing cascode current mirror is combined as a biasing circuit to provide proper voltage and stable output current for the op-amp structure. The proposed design is simulated in Cadence Virtuoso EDA tools software. The simulation results show the DC gain of 61.85 dB and phase margin (PM) of 88.34° with 0.5 pF load capacitor is achieved. Moreover, the slew rate and settling time of 120.125 V/µs and 20.3 ns are obtained, respectively. A low power consumption of 0.17 mW at supply voltage of 1.8 V indicates the low power is achieved in the circuit design. The proposed high speed low power CMOS op-amp is suitable for high-speed ADC applications. [ABSTRACT FROM AUTHOR]
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Titel: |
Design of high-speed low power CMOS operational amplifier utilizing 0.18-µm technology for ADC applications.
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Autor/in / Beteiligte Person: | Murad, S. A. Z. ; Bakar, F. A. ; Jasri, I. A. A. ; Zulkifli, T. Z. A. ; Marzuki, A. |
Quelle: | AIP Conference Proceedings; 2023, Vol. 2579 Issue 1, p1-9, 9p; Jg. 2579 (2023-09-20) 1, S. 1-9 |
Veröffentlichung: | 2023 |
Medientyp: | Konferenz |
ISSN: | 0094-243X (print) |
DOI: | 10.1063/5.0136074 |
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