An optimal low energy cost 4-bit absolute value detector with 55.5 FO4(1V) based on CMOS process.

Traditionally, the design of absolute value detectors has long delay, high energy consumption, and is not accurate enough. The design has been divided into two parts, first taking the absolute value and then comparing with the threshold value. More steps bring more errors and time and energy costs. Therefore, this paper hopes to give a new design that can optimize these problems. In the design, this paper simplifies the traditional two-step design method into one step, and directly compares the size by calculating the difference. In the design, the optimized mirror adder is used, combined with logic calculation and multiplexer (MUX for short), a new design scheme is formed. At the same time, by adjusting the size of the gate and the voltage of the power supply, the power consumption of the circuit is reduced by 68.16% without a significant increase in delay. Coupled with the reduction in the number of devices used in the entire circuit, the overall design in this paper has lower delay and lower energy consumption than traditional methods. [ABSTRACT FROM AUTHOR]

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