Output Resistance Scaling Model for Deep-Submicron Cmos Buffers for Timing Performance Optimisation.
In: Integrated Circuit & System Design; 2005, p329-336, 8p
Buch
Zugriff:
CMOS buffers driving high capacitive loads play an important role in determining the overall performances of present-day complex integrated circuits. Ad hoc optimisation techniques require effective models simple enough to enable the optimisation of multi-million gate circuits. However, due to size and supply voltage reduction, the behaviour of deep-sub micron devices may differ significantly from the conventional one and the classical models and techniques need to be improved or radically modified. In the paper the Authors show how the well-exploited assumption of a linear relationship between the channel width and the current meanly conducted during the switching transient may be incorrect for deep-submicron buffer transistors. As direct consequence, it follows that the common practice of widening the channel width of the MOSFET transistors may not lead to the expected results in terms of buffer output resistance reduction. On these bases, a novel expression to estimate the actual effect of a channel widening on the output resistance of CMOS buffer that agrees with HSPICE circuit simulations within 3% error is presented. [ABSTRACT FROM AUTHOR]
Copyright of Integrated Circuit & System Design is the property of Springer eBooks and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)
Titel: |
Output Resistance Scaling Model for Deep-Submicron Cmos Buffers for Timing Performance Optimisation.
|
---|---|
Autor/in / Beteiligte Person: | Paliouras, Vassilis ; Vounckx, Johan ; Verkest, Diederik ; Cappuccino, Gregorio ; Pugliese, Andrea ; Cocorullo, Giuseppe |
Quelle: | Integrated Circuit & System Design; 2005, p329-336, 8p |
Veröffentlichung: | 2005 |
Medientyp: | Buch |
ISBN: | 978-3-540-29013-1 (print) |
DOI: | 10.1007/11556930_34 |
Sonstiges: |
|