一种先进 CMOS 工艺下抗单粒子瞬态加固的与非门. (Chinese)
In: Journal of Harbin Institute of Technology. Social Sciences Edition / Haerbin Gongye Daxue Xuebao. Shehui Kexue Ban, Jg. 55 (2023-05-01), Heft 5, S. 114-121
academicJournal
Zugriff:
The development of advanced nano-integrated circuit processes has led to a decreasing threshold charge in microelectronic devices, resulting in an increased rate of soft errors caused by single-event effects in digital circuits. To enhance the radiation resistance of standard cells in integrated circuits, this paper proposes a NAND gate structure that is resistant to single-event transients (SETs). In the triple well process, by shorting the substrate and source of each NMOS transistor in the pull-down network, the radiation resistance of the NAND gate was effectively improved, and the hardening of the proposed NAND gate became more effective as the number of inputs increased. Particle incidence simulation experiments were performed by Sentaurus TCAD software in hybrid simulation mode. For the NMOS transistor connected to the output node, the three-dimensional physical model that has been calibrated by the process was used, and the Spice model provided by the manufacturer was adopted for other MOS transistors. Simulation results show that the proposed two-input NAND in 40 nm process could reduce the output voltage fluctuation amplitude in three-input cases at the linear energy transfer (LET) value of incidence particle of 10 MeV·cm²/mg. Besides, the effect of immunity to single particle incidence was achieved in the input mode with N 2 transistor closed. For the hardened three-input NAND gate, the output voltage disturbance could be reduced by up to 85.4% even in the “worst case”. Therefore, the proposed hardening method for NAND gate has a significant effect against SET. [ABSTRACT FROM AUTHOR]
先进纳米集成电路工艺的发展使得微电子器件翻转的阈值电荷不断降低, 导致数字电路中由单粒子效应引起的软错 误率增加。 为加强集成电路中标准单元的抗辐射特性, 本文提出了一种抗单粒子瞬态 (single-event transient, SET) 加固的与非 门结构。 在三阱工艺下, 通过将下拉网络中每一个 NMOS 管的衬底和源极各自短接, 便有效地提高了与非门抗辐射性能, 而 且随着输入端数目的增加, 本文提出的与非门加固效果更加明显。 利用 Sentaurus TCAD 软件的混合仿真模式进行粒子入射 仿真实验, 对于与输出节点相连的 NMOS 管采用经过工艺校准的三维物理模型, 其他 MOS 管采用工艺厂商提供的 Spice 模型。 结果显示:在 40 nm 工艺下, 当入射粒子线性能量传输 (linear energy transfer, LET) 值为 10 MeV·cm² / mg 时, 本文提出的 2 输入 与非门能够在 3 种输入的情况下降低输出电压扰动幅度。 其中在 N 2 管关闭的输入模式下, 达到了对单粒子入射免疫的效果; 对于 3 输入与非门, 即使在“最坏”输入的情况下, 也能使输出电压翻转幅度降低 85.4% 。 因此, 本文提出的与非门加固方法 起到了显著的抗单粒子瞬态效果。 [ABSTRACT FROM AUTHOR]
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Titel: |
一种先进 CMOS 工艺下抗单粒子瞬态加固的与非门. (Chinese)
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Autor/in / Beteiligte Person: | 柱, 史 ; 筱, 肖 ; 斌, 王 ; 博, 杨 ; 卢红利 ; 岳红菊 ; 刘文平 |
Zeitschrift: | Journal of Harbin Institute of Technology. Social Sciences Edition / Haerbin Gongye Daxue Xuebao. Shehui Kexue Ban, Jg. 55 (2023-05-01), Heft 5, S. 114-121 |
Veröffentlichung: | 2023 |
Medientyp: | academicJournal |
ISSN: | 1009-1971 (print) |
DOI: | 10.11918/202109131 |
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