Design of Low-Power CMOS VCO with Three Transistors NAND Gate and MOS Varactor.
In: Journal of the Institution of Engineers (India): Series B, Jg. 104 (2023-08-01), Heft 4, S. 851-858
Online
academicJournal
Zugriff:
Titel: |
Design of Low-Power CMOS VCO with Three Transistors NAND Gate and MOS Varactor.
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Autor/in / Beteiligte Person: | Kumar, Manoj |
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Zeitschrift: | Journal of the Institution of Engineers (India): Series B, Jg. 104 (2023-08-01), Heft 4, S. 851-858 |
Veröffentlichung: | 2023 |
Medientyp: | academicJournal |
ISSN: | 2250-2106 (print) |
DOI: | 10.1007/s40031-023-00898-9 |
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