Slurry Development Challenges and Solutions for Advanced Node Copper CMP
In: ECS Transactions, Jg. 18 (2009-03-06), Heft 1, S. 541-546
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Zugriff:
The R&D of Cu CMP started in the late 1980s but was fully implemented in the HVM in the late 1990s and early 2000. Cu CMP was fully implemented for the 130 nm nodes primarily in the Logic devices. In the decade following the Cu CMP introduction, it has grown and changed in significant ways. As of now Cu CMP is a main stay for most BEOL integration schemes and being applied to Memory, 3D and MEMS devices. The success of Cu CMP was due to many enabling events such as Ta barrier development, AMAT Mirra tool design and low selectivity barrier process. As we move from 130 nm nodes into more advanced nodes additional challenges have unfolded. Performance requirements have become quite stringent while CoO reduction pressures are mounting. While the 130 nm process required polishing of Cu, Ta and TEOS at high DF , moderate topography and moderate defects, for 32 nm and beyond polishing of multiple complex materials (like LK, ULK, ALD barriers, MHM, ARC and Copper) at very low DF with very low topography and defects is essential. These challenging needs for the advanced nodes require novel slurry development solutions. Both the Copper and Barrier layer slurries have changed over the decade. Abrasives have changed from Alumina and fumed silica to colloidal silica and coated particles. Significant change in chemistry design is required to address low DF polishing.
Titel: |
Slurry Development Challenges and Solutions for Advanced Node Copper CMP
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Autor/in / Beteiligte Person: | Mahulikar, Deepak |
Zeitschrift: | ECS Transactions, Jg. 18 (2009-03-06), Heft 1, S. 541-546 |
Veröffentlichung: | 2009 |
Medientyp: | serialPeriodical |
ISSN: | 1938-5862 (print) ; 1938-6737 (print) |
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