Multiple-Gate CMOS Thin-Film Transistor With Polysilicon Nanowire
In: IEEE Electron Device Letters, Jg. 29 (2008), S. 102-105
Online
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Zugriff:
An ultimately scaled multiple-gate CMOS thin-film transistor with a polysilicon (poly-Si) nanowire demonstrates feasibility for vertical integration using multiple active layers for application in the terabit memory era. The short-channel effects are suppressed using a multiple gate to wrap around the nanowire in devices with a size of a few tenths of a nanometer. The switching and output characteristics show high device performance without a crystallization process for the poly-Si nanowire.
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Multiple-Gate CMOS Thin-Film Transistor With Polysilicon Nanowire
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Autor/in / Beteiligte Person: | Kim, Changhoon ; Kim, Sungho ; Han, Jin-Woo ; Jae Sub Oh ; Lee, Hyunjin ; Kwang Hee Kim ; Choi, Yang-Kyu ; Gi Sung Lee ; Yun Chang Park ; Sang Cheol Jeon ; Im, Maesoon ; Hee Mok Lee ; Yu, Lee-Eun |
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Zeitschrift: | IEEE Electron Device Letters, Jg. 29 (2008), S. 102-105 |
Veröffentlichung: | Institute of Electrical and Electronics Engineers (IEEE), 2008 |
Medientyp: | unknown |
ISSN: | 1558-0563 (print) ; 0741-3106 (print) |
DOI: | 10.1109/led.2007.911982 |
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