A 15.5x-gain 0.29-mm2 CMOS readout circuit for 1.5-Mpixel 60-fps CMOS image sensor
In: Analog Integrated Circuits and Signal Processing, Jg. 108 (2021-01-18), S. 89-99
Online
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Zugriff:
An analog signal processing (ASP) circuit used for CMOS image sensor (CIS) readout is presented. The proposed ASP mainly includes a two-stage programmable gain amplifier (PGA), a sample-and-hold amplifier (SHA) merged by a pipelined analog–digital converter (ADC), and a digital-analog converter (DAC). Compared with conventional readout architecture, the proposed can provide finer gain, level shifting as well as offset calibrating function. A 1.5-Mpixel 60-fps CIS with the ASP is fabricated in a 0.13 μm 1P4M CMOS mixed signal process. The experiment results indicate the sensor can normally capture images without missing code. Moreover, the measured maximum gain error of the PGA is 1.6%, and the power dissipation is 16.5 mW for single ASP.
| Titel: |
A 15.5x-gain 0.29-mm2 CMOS readout circuit for 1.5-Mpixel 60-fps CMOS image sensor
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| Autor/in / Beteiligte Person: | Wang, Kunyu ; Zhou, Li ; Yang, Yang-Jun ; Zhang, Chengbin ; Cen, Gao ; Chen, Ming ; Chen, Jie ; Wenjing, Xu |
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| Zeitschrift: | Analog Integrated Circuits and Signal Processing, Jg. 108 (2021-01-18), S. 89-99 |
| Veröffentlichung: | Springer Science and Business Media LLC, 2021 |
| Medientyp: | unknown |
| ISSN: | 1573-1979 (print) ; 0925-1030 (print) |
| DOI: | 10.1007/s10470-020-01778-8 |
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