A Spurious and Oscillator Pulling Free CMOS Quadrature LO-Generator for Cellular NB-IoT
In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Jg. 29 (2021-12-01), S. 2098-2109
Online
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Zugriff:
A reconfigurable LO-generator (LOG) using an integer divider and a mixed-mode fractional divide-by-2.5 (Div2.5) is presented to generate a spurious and oscillator pulling free output spectrum without additional digital calibration for cellular narrowband Internet of Things (NB-IoT). The proposed LOG includes a fractional divider to mitigate the pulling effect between the oscillator and the power amplifier. The designed fractional Div2.5 consists of a digital Div2.5 core, a duty cycle corrector (DCC), and an I/Q generator (I/Q-GEN). An adaptive bias circuit (ADB) is applied to compensate for process, voltage, and temperature (PVT) variations on delay circuits of the DCC and the I/Q-GEN by adjusting the supply voltage. The designed LOG is fabricated in the 28-nm CMOS process while consuming 40 mW, including ADPLL, digitally controlled oscillator (DCO), local oscillator (LO) distribution buffers, and dividers at 2 GHz. The measured phase noise of the Div2.5 LOG generating 2-GHz carrier frequency is -146.3 dBc/Hz at a 10-MHz offset. The measured fractional spurious tones are below -90 dBc without oscillator pulling effects for the 1.6~2.1-GHz output frequency.
Titel: |
A Spurious and Oscillator Pulling Free CMOS Quadrature LO-Generator for Cellular NB-IoT
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Autor/in / Beteiligte Person: | Kim, Nam-Seog ; Choi, Jaewon |
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Zeitschrift: | IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Jg. 29 (2021-12-01), S. 2098-2109 |
Veröffentlichung: | Institute of Electrical and Electronics Engineers (IEEE), 2021 |
Medientyp: | unknown |
ISSN: | 1557-9999 (print) ; 1063-8210 (print) |
DOI: | 10.1109/tvlsi.2021.3105819 |
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