A 219-μW 1D-to-2D-Based Priority Encoder on 65-nm SOTB CMOS
In: 2018 IEEE International Symposium on Circuits and Systems (ISCAS), 2018
Online
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Zugriff:
Priority encoder (PE) is recognized as an indispensable component in the content-addressable memory. In this paper, two efficient architecture of 64-bit PE and 256-bit PE using 1D-array to 2D-array conversion (1D-to-2D) method are presented and implemented in a 65-nm Silicon-on-thin-buried-oxide (SOTB) CMOS process. The 1D-to-2D method is exploited because of its advantages in large-sized PE construction. The SOTB CMOS process is utilized because of its prominent advantages of low-power and high-performance configuration using back bias voltages. The measurement results at 1.2 V showed that a fabricated PE256 chip was fully operational at 45 MHz and consumed approximately 219 μW. Additionally, in sleep mode, the leakage power dropped as low as 0.34 μW at 0.6 V.
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A 219-μW 1D-to-2D-Based Priority Encoder on 65-nm SOTB CMOS
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Autor/in / Beteiligte Person: | Nguyen, Hong-Thu ; Pham, Cong-Kha ; Inoue, Katsumi ; Hoang, Trong-Thuc ; Nguyen, Xuan-Thuan |
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Zeitschrift: | 2018 IEEE International Symposium on Circuits and Systems (ISCAS), 2018 |
Veröffentlichung: | IEEE, 2018 |
Medientyp: | unknown |
DOI: | 10.1109/iscas.2018.8351406 |
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