65.6–75.2-GHz Phase-Controlled Push–Push Frequency Quadrupler With 8.3% DC-to-RF Efficiency in 40-nm CMOS

We present a 40-nm CMOS 70-GHz frequency quadrupler based on a phase-controlled push–push (PCPP) topology that provides high efficiency and harmonic suppression. Since MOSFETs in the PCPP stack turn off alternately, the quadrupler can provide high energy efficiency even for fourth-order frequency multiplication. One major problem related to even-order harmonic suppression was mitigated by using a transformer-based output amplifier with no degradation in energy efficiency. The fabricated quadrupler provides the 3-dB bandwidth and peak output power of 65.6–75.2 GHz and −0.2 dBm at 70 GHz, respectively, with an 8.9-dBm fundamental input power. The peak dc-to-RF efficiency was measured to be 8.3% with 11.4-mW dc power consumption, including an output amplifier. At 70 GHz, measured harmonic suppression was around 51.1, 41.0, and 43.1 dBc at first, second, and third harmonic frequencies, respectively.