A 3.8 GHz 153 Mb SRAM Design With Dynamic Stability Enhancement and Leakage Reduction in 45 nm High-k Metal Gate CMOS Technology
In: IEEE Journal of Solid-State Circuits, Jg. 44 (2009), S. 148-154
Online
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Zugriff:
A high-performance low-power 153 Mb SRAM is developed in 45 nm high-k Metal Gate technology. Dynamic SRAM PMOS forward-body-bias (FBB) and Active-Controlled SRAM VCC in Sleep are integrated in the design to lower Active-VCCmin and Standby Leakage, respectively. FBB improves the Active-VCCmin by up to 75 mV, and Active-Controlled SRAM VCC distribution tightened by 100 mV, both of which result in further power reduction. A 0.346 mum2 6T-SRAM bit-cell is used which is optimized for VCCmin, performance, leakage and area. The design operates at high-speed over a wide voltage range, and has a maximum frequency of 3.8 GHz at 1.1 V. The 16 KB Subarray was also used as the building block in on-die 6 MB Cache for Intel Core 2 Duo CPU in 45 nm technology.
Titel: |
A 3.8 GHz 153 Mb SRAM Design With Dynamic Stability Enhancement and Leakage Reduction in 45 nm High-k Metal Gate CMOS Technology
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Autor/in / Beteiligte Person: | Bhattacharya, Uddalak ; Wang, Yih ; Smits, K. ; Hong Jo Ahn ; Bohr, M. ; Chen, Zhanping ; Pavlov, Andrei ; Ng, Yong-Gee ; Hamzaoglu, Fatih ; Zhang, Kevin |
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Zeitschrift: | IEEE Journal of Solid-State Circuits, Jg. 44 (2009), S. 148-154 |
Veröffentlichung: | Institute of Electrical and Electronics Engineers (IEEE), 2009 |
Medientyp: | unknown |
ISSN: | 0018-9200 (print) |
DOI: | 10.1109/jssc.2008.2007151 |
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