An 18 mW 1800 MHz quadrature demodulator in 0.18 μm CMOS
In: 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315), 2003-06-25
Online
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Zugriff:
A demodulator has been designed which consists of a 3.6 GHz VCO, a 3.8 mA current-mode divider for the I/Q generation, and two single-ended input double-balanced mixers. The IC consumes 10 mA at 1.8 V, and has -114 dBc phase noise at 100 kHz offset, 40 dB image rejection, 14 dB DSB noise figure and 8.5 dBm IIP3.
Titel: |
An 18 mW 1800 MHz quadrature demodulator in 0.18 μm CMOS
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Autor/in / Beteiligte Person: | Pfaff, D. ; Huang, Q. |
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Zeitschrift: | 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315), 2003-06-25 |
Veröffentlichung: | IEEE, 2003 |
Medientyp: | unknown |
DOI: | 10.1109/isscc.2002.993026 |
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