Performance Analysis of Fully Depleted SOI Tapered Body Reduced Source (FD-SOI TBRS) MOSFET for Low Power Digital Applications

The fully depleted silicon-on-insulator metal oxide semiconductor field effect transistor (FD- SOI MOSFET) have been considered a promising candidate to extend scaling of planar CMOS technology beyond 100 nm. This technology has been used to reduce leakage current, parasitic capacitances, and fabrication complexity as compared to planar CMOS technology at 50 nm gate length. This paper presents the performance analysis of proposed Tapered Body Reduced Source (FD-SOI TBRS) MOSFET. The proposed structure consumes less chip area and better electrical performance as compared to conventional FD-SOI MOSFET. The proposed structure exhibits higher Ion to Ioff ratio when compared with conventional FD-SOI MOSFET. The structures were designed and simulated using the Cogenda device simulator.