A 5-GHz programmable frequency divider in 0.18-μm CMOS technology
In: Journal of Semiconductors, Jg. 31 (2010-05-01), S. 055004-55004
Online
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Zugriff:
A 5-GHz CMOS programmable frequency divider whose modulus can be varied from 2403 to 2480 for 2.4-GHz ZigBee applications is presented. The divider based on a dual-modulus prescaler (DMP) and pulse-swallow counter is designed to reduce power consumption and chip area. Implemented in the 0.18-μm mixed-signal CMOS process, the divider operates over a wide range of 1–7.4 GHz with an input signal of 7.5 dBm; the programmable divider output phase noise is −125.3 dBc/Hz at an offset of 100 kHz. The core circuit without test buffer consumes 4.3 mA current from a 1.8 V power supply and occupies a chip area of approximately 0.015 mm2. The experimental results indicate that the programmable divider works well for its application in frequency synthesizers.
Titel: |
A 5-GHz programmable frequency divider in 0.18-μm CMOS technology
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Autor/in / Beteiligte Person: | Zhiqun, Li ; Haiyong, Shu |
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Zeitschrift: | Journal of Semiconductors, Jg. 31 (2010-05-01), S. 055004-55004 |
Veröffentlichung: | IOP Publishing, 2010 |
Medientyp: | unknown |
ISSN: | 1674-4926 (print) |
DOI: | 10.1088/1674-4926/31/5/055004 |
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