A Robust Hardened Latch Featuring Tolerance to Double-Node-Upset in 28nm CMOS for Spaceborne Application
In: IEEE Transactions on Circuits and Systems II: Express Briefs, Jg. 67 (2020-09-01), S. 1619-1623
Online
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Zugriff:
Soft errors induced by high energy particles have been a severe concern in integrated circuits. Especially in advanced nanoscale technology nodes, the phenomenon of multi-node-upset caused by charge sharing is becoming a crucial issue. However, this problem remains a challenge as there are only few mitigation methods. This brief demonstrates a cost-efficient latch named CROUT featuring double-node-upset tolerance. Integrating coupled Schmitt-triggers and four always-on high-threshold transistors, CROUT is highly reliable in the presence of double-node-upset. To further validate this, a test chip was fabricated in the 28nm CMOS process and tested in a heavy-ion radiation environment. The experimental results indicated that the radiation tolerance is about 2x higher than the standard latches. Moreover, compared to other state-of-the-art multi-node-upset tolerant latches, its power-delay-product (PDP) is reduced by ~6x. The results show that our proposed latch is highly reliable and cost-effective for the space application, which further can be made into a standard cell to be integrated into large-scale circuits.
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A Robust Hardened Latch Featuring Tolerance to Double-Node-Upset in 28nm CMOS for Spaceborne Application
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Autor/in / Beteiligte Person: | Tahoori, Mehdi B. ; Tan, Chiyu ; Zhao, Yuanfu ; Li, Tongde ; Han, Jun ; Li, Yan ; Zeng, Xiaoyang ; Wang, Liang ; Cheng, Xu |
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Zeitschrift: | IEEE Transactions on Circuits and Systems II: Express Briefs, Jg. 67 (2020-09-01), S. 1619-1623 |
Veröffentlichung: | Institute of Electrical and Electronics Engineers (IEEE), 2020 |
Medientyp: | unknown |
ISSN: | 1558-3791 (print) ; 1549-7747 (print) |
DOI: | 10.1109/tcsii.2020.3013338 |
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