A 1.1 GHz 12 $\mu$A/Mb-Leakage SRAM Design in 65 nm Ultra-Low-Power CMOS Technology With Integrated Leakage Reduction for Mobile Applications
In: IEEE Journal of Solid-State Circuits, Jg. 43 (2008), S. 172-179
Online
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Zugriff:
A low-power, high-speed SRAM macro is designed in a 65 nm ultra-low-power (ULP) logic technology for mobile applications. The 65 nm strained silicon technology improves transistor performance/leakage tradeoff, which is essential to achieve fast SRAM access speed at substantially low operating voltage and standby leakage. The 1 Mb SRAM macro features a 0.667 mum2 low-leakage memory cell and can operate over a wide range of supply voltages from 1.2 V to 0.5 V. It achieves operating frequency of 1.1 GHz and 250 MHz at 1.2 V and 0.7 V, respectively. The SRAM leakage is reduced to 12 muA/Mb at the data retention voltage of 0.5 V. The measured bitcell leakage from the SRAM array is ~2 pA/bit at retention voltage with integrated leakage reduction schemes.
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A 1.1 GHz 12 $\mu$A/Mb-Leakage SRAM Design in 65 nm Ultra-Low-Power CMOS Technology With Integrated Leakage Reduction for Mobile Applications
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Autor/in / Beteiligte Person: | Lin, J. ; Kulkarni, Sarvesh H. ; Hafez Walid, M ; Wang, Yih ; Hamzaoglu, F. ; Bhattacharya, Uddalak ; Bohr, M. ; Coan, T. ; Jan, Chia-Hong ; Zhang, Kevin ; Kolar, Pramod ; Post, Ian R. ; Ng, Yong-Gee ; Wei, Liqiong ; Zhang, Ying ; Chen, Zhanping ; Hong Jo Ahn |
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Zeitschrift: | IEEE Journal of Solid-State Circuits, Jg. 43 (2008), S. 172-179 |
Veröffentlichung: | Institute of Electrical and Electronics Engineers (IEEE), 2008 |
Medientyp: | unknown |
ISSN: | 0018-9200 (print) |
DOI: | 10.1109/jssc.2007.907996 |
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