CMOS power amplifier design for cellular applications

A dual-mode and quad-band CMOS power amplifier (PA) in a standard 0.18-μm CMOS process is presented for GSM/EDGE (Global System for Mobile communications/Enhanced Data rates for GSM Evolution) applications in cellular and PCS (Personal Communications Service) bands. It is implemented with two integrated passive devices on a high-resistive Si substrate. Using two diodes in series, it can detect the strength of the RF signal and adaptively provide the dc bias for the gate of the amplifier in order to efficiently improve AM–AM characteristics. For linearization for AM–PM distortion, this work is focused on the nonlinear gate-drain capacitance (Cgd) in the common gate stage and shows that Cgd can be effectively linearized by adding an additional capacitor in series. The CMOS PA achieves 23% of power-added efficiency at an output power of 27.5 dBm at 1.8 GHz in EDGE mode and 55% at 870 MHz in GSM mode. The receiver band noise with a 100-kHz RBW (resolution bandwidth) at 20 MHz offset is −82 and −86 dBm for the GSM and EDGE modes, respectively. The proposed PAs meet the class E2 power requirement satisfying linearity specifications such as EVM (error vector magnitude) and ACPR (adjacent channel power ratio) for EDGE and GSM applications.