Mismatch Analysis of DTCs With an Improved BIST-TDC in 28-nm CMOS
In: IEEE Transactions on Circuits and Systems I: Regular Papers, Jg. 69 (2022), S. 196-206
Online
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Zugriff:
Nonlinearity of a digital-to-time converter (DTC) is pivotal to spur performance in DTC-based all-digital phase-locked-loops (ADPLL). In this paper, we characterize and analyze the mismatch of cascaded-delay-unit DTCs. Through an improved built-in-self-test (BIST) time-to-digital converter (TDC) assisted with phase-to-frequency detector (PFD), a measurement system of sub-half-ps accuracy is constructed to conduct the characterization. Fabricated in 28-nm CMOS, the DTC transfer functions are measured, and mismatches are compared against Monte-Carlo simulation results. The integral nonlinearity (INL) results are compared against each other and converted to the in-band fractional spur level when the DTC would be deployed in the ADPLL. The BIST-TDC system thus characterizes the on-chip delays without expensive equipment or complex setup. The effectiveness of adding a PFD into the ΔΣ loop is validated. The entire BIST system consumes 0.6mW with a system self-calibration algorithm to tackle the analog blocks' nonlinearities.
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Mismatch Analysis of DTCs With an Improved BIST-TDC in 28-nm CMOS
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Autor/in / Beteiligte Person: | Chen, Peng ; Martins, Rui P. ; Robert Bogdan Staszewski ; Mak, Pui-In ; Zhang, Feifei ; Yin, Jun |
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Zeitschrift: | IEEE Transactions on Circuits and Systems I: Regular Papers, Jg. 69 (2022), S. 196-206 |
Veröffentlichung: | Institute of Electrical and Electronics Engineers (IEEE), 2022 |
Medientyp: | unknown |
ISSN: | 1558-0806 (print) ; 1549-8328 (print) |
DOI: | 10.1109/tcsi.2021.3105451 |
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