A 529-μW Fractional-N All-Digital PLL Using TDC Gain Auto-Calibration and an Inverse-Class-F DCO in 65-nm CMOS
In: IEEE Transactions on Circuits and Systems I: Regular Papers, Jg. 69 (2022), S. 51-63
Online
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Zugriff:
This paper presents an ultra-lower-power (ULP) digital-to-time-converter (DTC)-assisted fractional-N all-digital phase-locked loop (ADPLL) suitable for IoT applications. A proposed hybrid time-to-digital converter (TDC) extends the vernier-TDC input range with little power overhead in order to overcome the stability issue in the conventional architectures. The hybrid TDC also facilitates a background gain calibration to achieve a stable in-band phase noise insensitive to process, voltage, and temperature (PVT) variations. The implementation of a buffer-cascaded DTC simplifies the design complexity of the fractional-N operation. The ADPLL also features a 200 μW low-phase-noise inverse-class-F (class-F⁻¹) digitally controlled oscillator (DCO) without the need of two-dimensional (2-D) capacitor tuning for frequency alignment of the fundamental and 2nd-harmonic. Fabricated in 65-nm CMOS, the ULP ADPLL prototype achieves 868 fs $ _{rms}$ jitter in a fractional-N channel when consuming only 529 μW, corresponding to a figure-of-merit (FoM) of -244 dB.
Titel: |
A 529-μW Fractional-N All-Digital PLL Using TDC Gain Auto-Calibration and an Inverse-Class-F DCO in 65-nm CMOS
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Autor/in / Beteiligte Person: | Martins, Rui P. ; Chen, Peng ; Meng, Xi ; Robert Bogdan Staszewski ; Mak, Pui-In ; Yin, Jun |
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Zeitschrift: | IEEE Transactions on Circuits and Systems I: Regular Papers, Jg. 69 (2022), S. 51-63 |
Veröffentlichung: | Institute of Electrical and Electronics Engineers (IEEE), 2022 |
Medientyp: | unknown |
ISSN: | 1558-0806 (print) ; 1549-8328 (print) |
DOI: | 10.1109/tcsi.2021.3094094 |
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