A 430 mW 16 b 170 MS/s CMOS pipelined ADC with 77.2 dB SNR and 97.6 dB SFDR

A 16-bit 170 MS/s pipelined ADC implemented in 0.18 μm CMOS process is presented in this paper. An improved digital calibration method and a linearized sampling front-end are employed to achieve a high SFDR. The enlarged full scale range makes it possible to obtain a high SNR with smaller sampling capacitors, thus achieving higher speed and low power. This ADC attains an SNR of 77.2 dBFS, an SFDR of 97.6 dBc for a 10 MHz input signal, while preserving an SFDR > 80 dBc up to 300 MHz input frequency. The ADC consumes 430 mW from a 1.8 V supply and occupies a 17 mm2 active area.