Energy-efficient CMOS voltage level shifters with single-$$\hbox {V}_{{DD}}$$ for multi-core applications
In: Analog Integrated Circuits and Signal Processing, Jg. 107 (2021), S. 629-635
Online
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Zugriff:
The never-ending demands for battery-powered applications are driven by technological advances in the field of low power digital CMOS circuits. The voltage level shifters are crucial primitives for Systems-on-Chip (SoC) applications and systems operating with different voltage domains. In this article, three single supply energy-efficient low-power voltage level shifters are proposed that are suitable for input/output (I/O) and chip core interfaces in multi-core applications. The proposed level shifters are designed based on buffer and current mirror structures. The circuits are implemented in 180 nm technology and simulated using Cadence Spectre with two different supply voltages. The simulated results show better improvement in energy and average power of 2 $$\times$$ , static power of 41.3 $$\times$$ and delay of 55.8 $$\times$$ @ 1.8 V than the existing level shifters. The voltage conversion range is from threshold voltage to I/O voltage level i.e, 580 mV to 3.3 V. The post-layout simulation confirms robustness of voltage level conversion of the proposed circuits. Due to a significant enhancement in delay, static power, energy and conversion range the proposed circuits are suitable for low-energy applications and low-power chip core-I/O interfacings.
Titel: |
Energy-efficient CMOS voltage level shifters with single-$$\hbox {V}_{{DD}}$$ for multi-core applications
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Autor/in / Beteiligte Person: | Chakrapani, Arvind ; Rajendran, S. |
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Zeitschrift: | Analog Integrated Circuits and Signal Processing, Jg. 107 (2021), S. 629-635 |
Veröffentlichung: | Springer Science and Business Media LLC, 2021 |
Medientyp: | unknown |
ISSN: | 1573-1979 (print) ; 0925-1030 (print) |
DOI: | 10.1007/s10470-020-01776-w |
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