Device Parameter-Based Analytical Modeling of Power Supply Induced Jitter in CMOS Inverters
In: IEEE Transactions on Electron Devices, Jg. 68 (2021-07-01), S. 3268-3275
Online
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Zugriff:
This article presents an analytical approach to determine jitter for a CMOS inverter in the presence of power supply noise (PSN). The deviation in the transition edge of the output signal from its ideal timing is modeled accurately for each transition. A power series method is used to solve differential equations for different regions of transistors during output transition. The PSN has been expressed in Taylor series expression, aids to derive closed-form equation for time interval error (TIE). The obtained results from the proposed methodology closely match with electronic design automation (EDA) simulator results and verified on 40 nm Taiwan Semiconductor Manufacturing Company (TSMC) and 28 nm United Microelectronics Corporation (UMC) foundries, demonstrating accurate modeling of jitter.
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Device Parameter-Based Analytical Modeling of Power Supply Induced Jitter in CMOS Inverters
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Autor/in / Beteiligte Person: | Jai Narayan Tripathi ; Shrimali, Hitesh ; Arora, Puneet |
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Zeitschrift: | IEEE Transactions on Electron Devices, Jg. 68 (2021-07-01), S. 3268-3275 |
Veröffentlichung: | Institute of Electrical and Electronics Engineers (IEEE), 2021 |
Medientyp: | unknown |
ISSN: | 1557-9646 (print) ; 0018-9383 (print) |
DOI: | 10.1109/ted.2021.3082106 |
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