A 35-39 GHz CMOS Linearized Receiver with 2 dBm IIP3 and 16.8 dBm OIP3 for the 5G Systems
In: 2019 14th European Microwave Integrated Circuits Conference (EuMIC), 2019-09-01
Online
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Zugriff:
A35-39 GHz linearized differential in-phase and quadrature components (I/Q) receiver (Rx) fabricated in 65-nm CMOS for 5G massive front-ends phased-array systems is introduced. The two linearization techniques, multi-gate transistor (MGTR) and splitting cascode transistors (SCTR) linearizers, are adopted at RF amplifier and down-conversion mixers respectively which greatly cancel the 3rd-order intermodulation (IM3) power with P 1dB , IP3, and 3rd-harmonic rejection ratio (RR3) enhancements. According to measurements at RF 38 GHz in normal/linearized modes, the IP 1dB /OP 1dB showed 6 dB/2.4 dB enhancement (IP 1dB improved from -19 to -13 dBm, and OP 1dB improved from -1.6 to 0.8 dBm.) with 3.6 dB conversion gain (CG) degeneration (18. 4 dB decreased to 14.8 dB). The power consumption is 62.5 mW. According to two-tone measurements, the IM3 power decreased 20-28dB with IIP3lOIP3 enhancement of 13 dB/9.4 dB (IIP3 improved from -11 to 2 dBm, and OIP3 improved from 7.4 to 16.8 dBm The maximum IF power with RR3 value 1dB , OIP3 values, significant IP 1dB , IP3, RR3 improvement with IM3 suppression. This linearized Rx is satisfactory for 5G massive front-ends phased-array systems.
| Titel: |
A 35-39 GHz CMOS Linearized Receiver with 2 dBm IIP3 and 16.8 dBm OIP3 for the 5G Systems
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| Autor/in / Beteiligte Person: | Chen, Chun-Nien ; Kuo, Tai-Yu ; Wang, Huei ; Chen, Ying |
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| Zeitschrift: | 2019 14th European Microwave Integrated Circuits Conference (EuMIC), 2019-09-01 |
| Veröffentlichung: | IEEE, 2019 |
| Medientyp: | unknown |
| DOI: | 10.23919/eumic.2019.8909517 |
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