Multi-stage dual replica bit-line delay technique for process-variation-robust timing of low voltage SRAM sense amplifier
In: Frontiers of Information Technology & Electronic Engineering, Jg. 16 (2015-08-01), S. 700-706
Online
unknown
Zugriff:
A multi-stage dual replica bit-line delay (MDRBD) technique is proposed for reducing access time by suppressing the sense-amplifier enable (SAE) timing variation of low voltage static random-access memory (SRAM) applications. Compared with the traditional technique, this strategy, using statistical theory, reduces the timing variation by using multi-stage ideas, meanwhile doubling the replica bit-line (RBL) capacitance and discharge path simultaneously in each stage. At a supply voltage of 0.6 V, the simulation results show that the standard deviations of the SAE timing and cycle time with the proposed technique are 69.2% and 47.2%, respectively, smaller than that with a conventional RBL delay technique in TSMC 65 nm CMOS technology (Taiwan Semiconductor Manufacturing Company, Taiwan).
Titel: |
Multi-stage dual replica bit-line delay technique for process-variation-robust timing of low voltage SRAM sense amplifier
|
---|---|
Autor/in / Beteiligte Person: | Shoubiao, Tan ; Li, Zheng-ping ; Tao, Youwu ; Chen, Junning ; Peng, Chunyu ; Lu, Wen-juan |
Link: | |
Zeitschrift: | Frontiers of Information Technology & Electronic Engineering, Jg. 16 (2015-08-01), S. 700-706 |
Veröffentlichung: | Zhejiang University Press, 2015 |
Medientyp: | unknown |
ISSN: | 2095-9230 (print) ; 2095-9184 (print) |
DOI: | 10.1631/fitee.1400439 |
Schlagwort: |
|
Sonstiges: |
|