An Analog CMOS Implementation for Multi-layer Perceptron With ReLU Activation

This paper presents an analog circuit comprising a multi-layer perceptron (MLP) applicable to the neural network(NN)-based machine learning. The MLP circuit with rectified linear unit (ReLU) activation consists of 2 input neurons, 3 hidden neurons, and 4 output neurons. Our MLP circuit is implemented in a 0.6 μ m CMOS technology process with a supply voltage of ± 2.5 V. An experimental case is conducted to demonstrate the feasibility and effectiveness of the MLP circuit. The simulation results show that our MLP circuit has a power dissipation of 200mW, a wide range of working frequency from 0 to 1MHz, and a moderate performance in terms of the error ratio.